Cornell University Unit Name

"Development of Silicon Microstrip Sensor Modules"

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The baseline tracker design for the SiD detector concept takes advantage of the machine characteristics of the ILC to achieve a major reduction in material compared to previous large tracking systems based upon silicon microstrips. This requirement, considered essential for silicon tracking by all of the detector concepts, is realized in this design by the elimination of many components that have been essential in previous similar detectors. The other critical requirements for any large-scale silicon tracker; modularity and ease of mass production; arise naturally in this design by the use of very short (single sensor), monolithically-constructed, universal modules built from components mass produced by outside vendors. Progress to date consists of development of the detector module design (primarily at SLAC), and development of the overall tracker design that accommodates them (primarily at Fermilab). However, establishing the viability of this novel concept will demand significant new research and development efforts in order to establish a proof of principle in the form of a complete prototype detector module by 2007.

The key element in mass reduction is the complete elimination of hybrid electronic circuit boards that have been required in the past to service the front-end readout chips. This is achieved by bump-bonding the readout chips directly to the face of the silicon sensor, which leads to the need for several new developments in order to produce a working prototype:

• The development of bump-bondable silicon microstrip sensors that use a double-metal layer to connect a high-density bump-bonding array to the readout strips. Issues of capacitance, crosstalk and robustness to bump-bonding will have to be addressed. SLAC has begun the process of discussing the design with vendors and funds will be required in order to produce first prototypes for testing in 2006.
• The development of readout chips that bump-bond directly to the sensors. A first, small-scale prototype of this chip; a variant of the KPiX chip designed at SLAC for the SiD silicon-tungsten calorimeter; has been submitted and will be received for testing before the end of calendar year 2005. This chip uses analog storage cells and a pulsed power scheme to provide a beam-crossing stamp for each hit together with the quiet conditions during acquisition and low heat generation required by the direct mounting of the chip on the face of the silicon sensors. Future versions of this chip to be developed at SLAC during 2006 will need to be further differentiated from their calorimeter counterparts and will thus require significant funding and effort. It is expected that UC Davis will play an important role in the development of bump-bonding techniques required for the monolithic assembly of the modules.
• The development of flexible power and readout cables along with techniques for mechanical and electrical connection of the cables directly to the face of the silicon. While these cables are relatively simple, a safe and reliable scheme for low impedance connection of these cables directly to the silicon is required, since a double-metal layer on the silicon itself completes the connection of power and readout traces on the cable to the KPiX chip. In order to develop suitable techniques, a prototype cable must be designed alongside the silicon sensors during 2006, presumably at SLAC.

Finally, the routing of power and control signals between the cables and the readout chips via the double-metal layer of the silicon sensors creates new design issues for the sensors, as well unique issues for the grounding and filtering scheme for the modules. Although the digital portion of the chips are largely quiet during passage of the bunch train, it must be demonstrated that separate hybrid electronic circuit boards can be eliminated without incurring significant noise and crosstalk. It is this key point that must be proven with a complete and working prototype in order to prove the viability of the SiD tracker design.

The key elements in ensuring that the tracker modules are simple, inexpensive and easy to mass produce are the simplicity of the assembly process and the mass-producibility of individual components. The former arises naturally from the monolithic composition of a single detector module: a single silicon sensor with its own surface-mounted chip and cable attached to a simple support frame. The final challenge then is the design of a support frame that will be both light and stiff and can be mass produced by standard industrial processes. An initial design for this frame has been developed at SLAC, and must be developed further in cooperation with the overall mechanical design of the tracker at Fermilab so that prototypes can be obtained for assembly of a complete working sensor module. This will require a significant design effort and funding for tooling to produce prototypes in 2006 or 2007.

To date, support for this project has been minimal and has consisted primarily of manpower, sufficient only for producing initial designs. Real progress towards a working prototype has been made in 2005 by participation in the development of the tracking variant of the KPiX chip for the calorimeter at SLAC. However, a major increase in funding for this effort will be required in order to establish the viability of the baseline SiD tracker design with the production of working prototypes in the next two to three years.

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Please address the following questions in your statement.

• What are the goals of this R&D project. How does this R&D project address the needs of one or more of the detector concepts?

• If there are multiple institutions participating in this project, please describe the distribution of responsibilities.

• Are there significant recent results?

• What are the plans for the near future(about 1 year)? What are the plans on a time scale of 2 to 3 years?

• Are there critical items that must be addressed before significant results can be obtained from this project?

• Is the support for this project sufficient? Are there significant improvements that could be made with additional support?